The present invention relates to a digital radio communication system and, more particularly, to a demodulator of the digital radio communication system.
A digital radio communication system has a factor such as fading which degrades line quality. In order to remedy the system from such line quality degradation, in addition to a current line, a spare line is arranged.
FIG. 4 shows a digital radio communication system having a current line and a spare line.
A signal on the current line is input to an antenna 31a, and then frequency-converted to an IF (intermediate frequency) band by a receiver 32a. The signal is demodulated and subjected to signal equalization, error correction, and the like by a demodulator 33a. The resultant data becomes a current data signal 36a, and is output to a non-break switch 34. Similarly, a signal on the spare line passes through an antenna 31b, a receiver 32b, and a demodulator 33b. The resultant signal becomes a spare data signal 36b, and is output to the non-break switch 34.
Line quality degradation signals 38a and 38b are output from the demodulators 33a and 33b, and these signal are input to a switching controller 35. A switching control signal 37 is output from the switching controller 35, and this signal is input to the non-break switch 34.
The switching controller 35 receives the line quality degradation signals 38a and 38b to monitor line quality. When the switching controller 35 receives neither the line quality degradation signals 38a and 38b, the switching control signal 37 controls the non-break switch 34 to cause the non-break switch 34 to select the current data signal 36a. As a result, the non-break switch 34 outputs the current data signal 36a as transmitted data.
However, when the switching controller 35 receives the line quality degradation signal 38a from the demodulator 33a, the switching control signal 37 output at this time controls the non-break switch 34 to switch the current data signal 36a to the spare data signal 36b and output the spare data signal 36b. When the line quality degradation signal 38a is not input to the switching controller 35, the non-break switch 34 switches the spare data signal 36b to the current data signal 36a, thereby setting the original state.
Note that, when the line quality degradation signal 38b is output from the demodulator 33b, the above switching operation is not performed, and the non-break switch 34 is controlled to keep outputting the current data signal 36a.
FIG. 5 shows a demodulator used in a conventional digital radio communication system. The demodulator is constituted by a demodulation circuit 11, a signal processing circuit 12, and a decision equalizer 13.
The demodulation circuit 11 receives an intermediate-frequency signal input to an input terminal 1 to demodulate the intermediate-frequency signal to a baseband range and A/D-convert the intermediate-frequency signal, thereby outputting a digital signal.
The decision equalizer 13 uses a transversal filter to equalize an inter-code interference component contained in the digital signal input to the demodulation circuit 11, and the equalized signal is determined and then output as a determination signal 61.
The signal processing circuit 12 receives the determination signal 61 to establish frame synchronization, insert and extract a redundancy bit, perform error correction, and the like. The signal processing circuit 12 reproduces and outputs a data signal transmitted from the transmitting side. The reproduced data signal is output from an output terminal 2.
In an error correction process in the signal processing circuit 12, syndrome or parity pulses corresponding to the number of errors of the data signal are generated. These pulses are counted to estimate the number of errors occurring on a line. When the number of errors becomes larger than a predetermined error rate, an error rate alarm signal is output as a line quality degradation signal. This signal is output from an alarm output terminal 3.
The decision equalizer 13 will be described below in detail.
The decision equalizer 13 is constituted by a forward tap 14, a central tap 15, a backward tap 16, an adder 17 for adding outputs from the taps to each other, a main signal determination circuit 18 which receives an equalized signal output from the adder 17 to output the determination signal 61, and a subtracter 19 which receives the equalized signal and the determination signal 61 to output an error signal 62 (E) representing a difference between these signals.
The forward tap 14 is constituted by a multiplier 27a, a multiplier 28a, an integrator 29a, and a delay circuit 30a. The digital signal output from the demodulation circuit 11 is input to the forward tap 14, input to the central tap 15 through the delay circuit 30a, and input to the multipliers 27a and 28a. The multiplier 27a calculates the product between the digital signal and the error signal 62, and the product is integrated by the integrator 29a, thereby generating a forward tap coefficient serving as the correlation value of both the signals. The product between the forward tap coefficient and the digital signal is calculated by the multiplier 28a. In this manner, the digital signal which is not equalized is weighted by the forward tap coefficient to form a forward equalization signal, and this signal is output to the adder 17.
The central tap 15 is constituted by a multiplier 27b, a multiplier 28b, and an integrator 29b. A delay signal input to the central tap 15 through the delay circuit 30a is input to the multipliers 27b and 28b. The multiplier 27b calculates the product between the delay signal and the error signal 62, and this product is integrated by the integrator 29b, thereby generating a central tap coefficient serving as the correlation value between both the signals. The product between the central tap coefficient and the delay signal is calculated by the multiplier 28b. In this manner, the digital signal which is not equalized is weighted by the central tap coefficient to form a central equalization signal, and this signal is output to the adder 17.
The backward tap 16 is constituted by a multiplier 27c, a multiplier 28c, an integrator 29c, and a delay circuit 30b. The determination signal 61 output from the main signal determination circuit 18 is input to the backward tap 16 and input to the multipliers 27c and 28c through the delay circuit 30b. The multiplier 27c calculates the product between the delay determination signal and the error signal 62, and this product is integrated by the integrator 29c, thereby generating a backward tap coefficient serving as the correlation value between both the signals. The product between the backward tap coefficient and the delay determination signal is calculated by the multiplier 28c. In this manner, the delay determination signal is weighted by the backward tap coefficient to form a backward equalization signal, and this signal is output to the adder 17.
The adder 17 receives the forward equalization signal, the central equalization signal, and the backward equalization signal and adds them to each other, thereby outputting an equalized signal from which an inter-code interference component contained in an input to the decision equalizer 13 is removed.
The main signal determination circuit 18 receives the equalized signal output from the adder 17 and compares the equalized signal with a transmitted signal with respect to a signal point to estimate the most reliable value, and the main signal determination circuit 18 outputs the signal having the most reliable value as the determination signal 61.
The subtracter 19 subtracts the determination signal 61 from the equalized signal output from the adder 17 to calculate a difference therebetween, and the subtracter 19 outputs the error signal 62 serving as an equalization residue of the difference.
The operation of the demodulator in the conventional digital radio communication system will be described below.
When frequency non-selective fading occurs in a space, a reception field strength decreases to generate errors in transmitted data. As a decrease in receiving field strength is large, an error rate increases. When the error rate exceeds a predetermined value, a carrier reproducing circuit of the demodulator or the tap control circuit of the equalizer are diverged. In this case, the demodulator is set in an asynchronous state, and the data signal is set in an interrupt state.
In the demodulator in the conventional digital radio communication system, an error rate alarm signal generated by a signal processing circuit is used as a circuit switching condition. When the error rate is equal to or larger than a predetermined threshold value before a data signal is set in an interrupt state, a current line is switched to a spare line. This threshold value is determined depending on a speed at which fading becomes deep or on the quality required in data transmission.
As described above, when an error occurs in the current line due to frequency non-selective fading, the current line is switched to the spare line before the data is set in an interrupt state. For this reason, line quality having an error rate lower than a predetermined error rate can be kept.
As fading occurring in a space, in addition to the frequency non-selective fading which decreases a reception field strength, a frequency selective fading which causes inter-code interference is known.
The operation of the demodulator in the conventional system when the frequency selective fading occurs will be described below.
The forward tap 14, the central tap 15, and the backward tap 16 in the decision equalizer 13 in FIG. 5 respectively adjust tap coefficients in accordance with the magnitude of inter-code interference to cancel out the inter-code interference. In this case, the backward tap 16 uses the determination signal 61 as its input signal. More specifically, the determination signal 61 is obtained by determining the equalized signal. Even when inter-code interference occurs in a signal which is not equalized, an original signal is faithfully reproduced, provided that an equalization residue is small. However, when the inter-code interference increases to exceed a threshold value, erroneous determination is performed. When this erroneous determination is performed, a determination error larger than the equalization residue is added to the original signal.
The above operation will be described with reference to FIG. 6.
Referring to FIG. 6, (a) represents a signal point in a binary phase-shift keying (BPSK) scheme, and (b) represents a received signal which receives small inter-code interference. In this case, since an equalization residue does not exceed a threshold value, a main signal determination circuit correctly determines an equalized signal to reproduce a transmitted signal. As a result, the equalization residue is completely removed. In FIG. 6, (c) represents a received signal which receives large inter-code interference. In this case, since an equalization residue exceeds the threshold value, the main signal determination circuit erroneously determines the equalized signal, and a large determination error occurs.
When large inter-code interference which causes the backward tap 16 to operate occurs, a backward tap coefficient has a large value, and a determination error occurs. The erroneous value adversely affects an output from the backward tap, and this value is fedback, thereby causing so-called erroneous propagation to occur. When the erroneous propagation occurs, errors continuously occur, and the tap control circuit or the like of the equalizer is immediately diverged. The divergence of the equalizer caused by this erroneous propagation is generated at a speed considerably higher than the divergence of a demodulator or equalizer caused by the decrease in reception field strength. For this reason, when an error alarm signal is generated, data is immediately set in an interrupt state, and data cannot be protected by a switching operation between lines in time.